logic level中文是什么意思

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中文翻譯
造句

羅輯電平
邏輯電平，邏輯級
邏輯級

logic n. 1.邏輯，理論學。 2.推理[方法]；邏輯性，條理 ...
level n. 1.水平儀，水準儀；水準測量。 2.水平線，水平面 ...
assertion-level logic 斷言級邏輯，命題邏輯
binary logic level 二進制邏輯電平
four-level logic 四級邏輯
gate level logic simulation 門級邏輯模擬
gate-level logic simulation 門級邏輯模擬
hierarchical logic high level 分級邏輯高電平
high level logic 高電平邏輯電路
high level transistor logic 高電平晶體管晶體管邏輯
hll high level logic 高電平邏輯（電路）
level logic circuit 電平邏輯電路
lll low level logic 低電平邏輯（電路）
logic level band 邏輯電平帶
logic level indicator 邏輯電平指示器，邏輯級指示器; 邏輯級指示器
logic level translator 邏輯電平轉換器
logic nesting level number 邏輯嵌套級編號
logic-level shifter 邏輯水平位移器
low level logic 低電平邏輯
low-level logic 低電平邏輯
low-level logic circuit 低電平邏輯電路
meta-level logic 元級邏輯
n-level logic n級邏輯
negative logic level 負邏輯電平
nll negative logic level 負邏輯級

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例句與用法

Logic level indicator
邏輯電平指示器
Specification for analogue voltage ranges and logic levels for mains operated nuclear instruments
電源控制的核儀表的模擬電壓范圍和邏輯電平規范
When the keyboard or mouse wants to send information , it first checks the clock line to make sure it ' s at a high logic level
當鍵盤或者鼠標想發送數據時，它首先必須檢查時鐘線，確認它處于高電平。
The focus of our research in the low - power design of viterbi decoders is reduction of dynamic power dissipation at logic level in the standard cell design environment
從這里發掘功耗的潛力是很大的,主要通過優化算法、優化邏輯結構來實現。
Functions of logic synthesis are to transform and optimize the combinational logic functions and produce the pure logic level structural description
邏輯綜合的功能是對組合邏輯函數的描述進行轉換和優化，生成與邏輯功能描述等價的優化的邏輯級純結構描述。
Based on java concept , j2ee renders a type of high - level api independent of realization which implements a separation of application in logic level and system level
J2ee規范基于java概念，它提供的獨立于實現的高層api ，能夠實現應用程序邏輯層與系統層的分離。
The hierarchy provided by . net template can be divided to system framework level , data access level , business logic level , business presentation level and user interface level
. net模板給出了企業級分布式應用程序的層次結構，分為系統框架層、數據訪問層、業務規則層、業務外觀層和用戶界面層。
The thesis researches on the methodology for energy efficient soc design . soc has several design levels according to the design flow . the thesis covers on the higher levels including system level , software level , and synthesizable logic level
本文主要從可綜合的邏輯層以上的設計層次來進行soc低功耗設計方法論的研究，這些層次與工藝無關，包括系統設計、軟件設計和可綜合邏輯設計層次。
Beginning with software component technology , a software - bus - architecture - based special software development model is designed . the key technology such as system structure , logic levels , communication structure and application programming inerface ( api ) of software bus are detailedly described
本文從軟構件技術出發,提出了一種基于軟件總線體系結構的專用軟件開發模式,詳細討論了該系統的體系結構和邏輯層次、軟總線的通信結構以及總線api等關鍵技術。
These research works include presenting the high performance realization techniques for all of the usually basic functional units at the logic level , the basic rules and experiences of how to realize the high performance digital circuits by fpga or standard cells
所做的研究工作包括：運用邏輯平衡的思想提出了常用的基本運算單元的高性能解決方案，分析了用fpga實現高速數字電路的基本理論方法，研究了用標準單元實現高速數字電路的基本理論方法。

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百科解釋

In digital circuits, a logic level is one of a finite number of states that a signal can have. Logic levels are usually represented by the voltage difference between the signal and ground (or some other common reference point), although other standards exist.

詳細百科解釋